1. Field of the Invention
The present invention relates generally to integrated circuit testing, and more specifically to a time filter that delays static entry into an integrated circuit test mode.
2. Description of the Prior Art
Entry into a test mode or special operating modes for integrated circuits is often accomplished through either dynamic entry or static entry. Dynamic entry into a test mode is accomplished by clocking and latching the required test mode condition into the device being tested. The clocking and latching mechanism of dynamic entry offers the advantage of keeping all of the integrated circuit pins free for usage even after the test mode has been entered. However, a disadvantage of dynamic entry is that the test mode may be accidentally entered if the test mode condition is latched into the device when the test mode is not desired.
Static entry into a test mode is accomplished by supplying a static super voltage to one or more pins of the device being tested for the duration of the test mode. Static entry into a test mode is practical when it is not a requirement that all integrated circuit pins remain available for use during a test mode. For example, during a test mode where all the wordlines of a memory device are turned on, some, but not all, of the pins may be available for use. Additionally, entry into a parallel test mode where multiple words of data are accessed simultaneously speeds up testing and also frees up the use of some functional pins. However, a drawback of static test mode entry is that unintentional entry into a test mode can result from overshoots or undershoots on pins during normal operation in noisy systems.
In spite of the problems associated with static entry into a test mode, the difficulties apparent with dynamic entry into a test mode may be more problematic. Accidental dynamic entry into a test mode occurs as a result of clocking and then latching the required test mode condition into the device. This can also occur upon power up of the device. Because the test mode condition is latched in, it is difficult to exit a test mode once accidentally entered. On the other hand, accidental static entry into a test mode may be exited by simply removing the super voltage to the appropriate pins. The advantages of static entry make it desirable to determine a way to prevent unintentional static entry into a test mode.